FIG. 4 shows a block diagram of a prior art semiconductor IC tester. Timing data TS and pattern data PAT are read, respectively, from a timing part 12 and a pattern part 13 of a pattern generator 11 every test cycle. The timing data TS consisting of 10 bits for instance is supplied to a rate generator 14 and timing memories 15.sub.1 -15.sub.6. A reference timing signal at the test cycle corresponding to the timing data TS is generated from the rate generator 14 and is supplied to delay circuits 17.sub.1 -17.sub.6 via gates 16.sub.1 -16.sub.6. Moreover, the timing data TS is used as an address of timing memories 15.sub.1 -15.sub.6 and the delay data are read therefrom to set delay times in the delay circuits 17.sub.1 -17.sub.6. Timings in the test cycle are decided depending on the amount of the delay times in the delay circuits 17.sub.1 -17.sub.6.
The reference timing signal thus delayed in these delay circuits 17.sub.1 -17.sub.6 becomes six different clocks, i.e., the first to sixth clocks. The first clock is supplied to two AND circuits 18.sub.1 and 18.sub.2. The second clock is supplied to two AND circuits 18.sub.3 and 18.sub.4. The third clock is supplied to three AND circuits 18.sub.5, 18.sub.6, and 18.sub.7. The fourth clock is supplied to an AND circuit 18.sub.8. The fifth and sixth clocks are provided to comparators as strobe signals.
The contents of a waveform memory 19 are read by using the pattern data PAT as an address. The data are read from the first section to the eighth section of the waveform memory 19. These sections are represented by 0, 1, N, P, L, H, Z, and X in FIG. 4. One of the sections is specified by the three bits A, B, and C of the pattern data PAT. The first drive-high data T1S, the first drive-low data T1R, the second drive-high data T2S, the second drive-low data T2R, the third drive-high data T3S, the third drive-low data T3R, driver enable data T3L, driver disable data T4T, expected-high data EXH, and expected-low data EXL are respectively read from the specified section in the waveform memory 19.
The contents of the waveform memory 19 vary as waveforms generated are different, like NRZ (nonreturn to zero) waveform, NRZI (nonreturn to zero inverted) waveform, RZ (return to zero) waveform, RZI (return to zero inverted) waveform, XOR (exclusive OR) waveform, XORI (exclusive OR inverted) waveform, and etc. That is, a desired waveform is generated corresponding to the contents in the waveform memory 19.
Each output of the AND circuits 18.sub.1, 18.sub.3 and 18.sub.5 is supplied to a set terminal S of a first flip-flop 22 via an OR circuit 21. Each output of the AND circuits 18.sub.2, 18.sub.4 and 18.sub.6 is supplied to a reset terminal R of the first flip-flop 22 via an OR circuit 23. The output of the first flip-flop 22 is connected to an I/O pin of a device under test 26 through a driver 24 and a test pin 25.sub.i of the IC tester. In this example, the I/O pin of the IC device under test 26 functions both an input pin and an output pin, as is well known in the art. The output of the AND circuit 18.sub.7 is supplied to a set terminal S of a second flip-flop 77, and the output of the AND circuit 18.sub.8 is supplied to a reset terminal R of the second flip-flop 77. The output of the second flip-flop 77 is supplied to an enable control terminal of the driver 24.
The test pin 25.sub.i is also connected to an inverting input of a first comparator 27 and a non-inverting input of a second comparator 28. An output voltage of the device under test 26 through the test pin 25.sub.i is compared with a high threshold voltage V.sub.H and a low voltage threshold V.sub.L by the comparator 27 and 28, respectively. These compared results are sampled in the first and second comparators 27 and 28 by the strobes formed of the fifth and sixth clocks from the delay circuits 17.sub.5 and 17.sub.6. The outputs of the first and second comparators 27 and 28 are ANDed with the expected-high data EXH and the expected-low data EXL derived from the waveform memory 19 at AND circuits 31 and 32, respectively. The outputs of the first and second comparators 27 and 28 are also supplied to an OR circuit 33, and the output of the OR circuit 33 is ANDed with the expected-high data EXH and the expected-low data EXL at an AND circuit 34. Finally, the outputs of the AND circuits 31, 32, and 34 are supplied to an OR circuit 35.
In the case of applying the RZ waveform to the device under test 26, the contents of the waveform memory 19 are arranged as shown in FIG. 4. Three bits (PATA, PATB, PATC) of the pattern data from the pattern generator 11 are used as an address of the waveform memory 19. The least significant bit PATA mainly decides a waveform data. That is, when the PATA is logic 1, the waveform data is logic 1, and when the PATA is logic 0, the waveform data is logic 0. The I/O switch of an I/O pin is determined by the most significant bit PATC in the pattern data. That is, when a specific test pin of the device under test is used as an output pin (compare cycle), the PATC is logic 1, and otherwise logic 0. In the case of the compare cycle, expected data are determined by two bits of PATA and PATB as follows. The expected data is low L when PATA is 0 and PATB is 0. The expected data is high H when the PATA is 1 and the PATB is 0. The expected data is high impedance Z when the PATA is 0 and the PATB is 1. The expected data is "don't care X" when the PATA is 1 and the PATB is 1.
In the example of data arrangement in the waveform memory 19 shown in FIG. 4, and when the PATA of the pattern data is 1 and 0 as shown in FIG. 5A, the test signals are generated as follows. In either situation of the pattern data 1 or 0, the driver enable data T3L read from the waveform memory 19 is 1. The second flip-flop 77 is set beforehand through the AND circuit 18.sub.7 according to the timing of the clock from the delay circuit 17.sub.3. As a result, the driver 24 is enabled. When the PATA is 1, the first drive-high data T1S, which is 1, is read and the first flip-flop 22 is set by the T1S by the timing of the clock from the delay circuit 17.sub.1 as shown in FIG. 5B. Moreover, the second drive-low data T2R, which is also 1, is read and the first flip-flop 22 is reset by the timing of the clock from the delay circuit 17.sub.3 as shown in FIG. 5C. As a consequence, the driver 24 is driven by the RZ waveform shown in FIG. 5D and this RZ waveform is applied to an I/O pin of the device under test 26. When the PATA is 0, both T1S and T2R are 0, as shown in the waveform memory 19 of FIG. 4, so the input waveform to the driver 24 maintains a low level as shown in FIG. 5D.
When the I/O pin of the drive under test 26 is used as an output pin, the output impedance of the driver 24 is set to be infinite by resetting the second flip-flop 77 and disabling the driver 24. Under such condition, signals output from the device under test 26 through the I/O pin are supplied to the test pin 25.sub.i and are compared in the comparators 27 and 28 with the high threshold voltage V.sub.H and the low threshold voltage V.sub.L. The threshold voltages V.sub.H and V.sub.L are selected as shown in FIG. 5E. When the input voltage V is larger than V.sub.H, the output of the comparator 27 becomes low and the output of the comparator 28 becomes high. When the input V is smaller than V.sub.H and larger than V.sub.L, the output of the comparator 27 becomes high and the output of the comparator 28 becomes also high. When the input V is smaller than V.sub.L, the output of the comparator 27 becomes high and the output of the comparator 28 becomes low.
The compared results in the comparators 27 and 29 are sampled by the strobes of the same timing from the delay circuits 17.sub.5 and 17.sub.6, and ANDed with expected-high data EXH and expected-low data EXL read from the waveform memory 19 by the AND circuits 31 and 32. When the expected data is low, expected-low data EXL from the waveform memory 19 is 1. When the expected data is high, expected-high data EXH from the waveform memory is 1. When the expected data is high impedance output Z, EXL and EXH are both 1. When the expected data is "don't care X", EXL and EXH are both 0. As a result, when the expected data is high and the input V is smaller than threshold V.sub.H, the output of the AND circuit 31 becomes high level showing a failure of the output of the device under test 26. When the expected data is low and the input V is larger than V.sub.L, the output of the AND circuit 32 becomes high level showing a failure of the output of the device under test 26. When the expected data is high impedance and the input V is not in a high impedance state, the output of the AND circuit 34 becomes high level indicating a failure in the output signal of the device under test 26. Failure signals from the AND circuits 31, 32 and 34 are also provided to the OR circuit 35.
The foregoing is a mechanism to apply test patterns to the device under test 26 and to perform a GO/NO-GO decision of the output of the device under test 26 is provided at each test pin of the IC tester. Therefore, the IC tester usually has a large number of circuit configurations as shown in FIG. 4 corresponding to the number of pins for prospective IC devices to be tested. If, for example, the device under test 26 includes a hundred I/O pins, the IC tester must includes at least a hundred circuit configuration shown in FIG. 4 to test all the I/O pins through a process as describe above.
In the conventional IC tester, a test can be performed at a faster speed than the maximum speed of the IC tester by arranging the circuit connection as shown in FIG. 6. In FIG. 6, like parts corresponding to those in FIG. 4 are identified by the same reference numerals. The odd number test pin 25.sub.i and an even number pin 25.sub.i+1 adjacent to the odd number pin are connected as follows. The outputs of two OR circuits 21, the outputs of two OR circuits 23, the outputs of two AND circuits 187, and the outputs of two AND circuits 18.sub.8 are connected in parallel. Further, all inputs of comparators 27 and 28 are connected to receive an output signal from the device under test through the I/O pin 25.sub.i. As shown in FIG. 6, only the odd number test pin 25.sub.i is connected to the I/O pin of the device under test 26. The test patterns are applied to the device under test 26 as follows. Clocks and strobes to the odd number test pin 25.sub.i are generated in the first half of test cycle T, while clocks and strobes corresponding to the even number test pin 25.sub.i+1 (now not used) are generated in the latter half of test cycle T. Because tests are performed two times in one test cycle T, the double-speed test can be achieved.
In the double-speed test of the conventional structure shown in FIG. 6, only the IC device which has a number of I/O pins equal to or less than a half of the number of test pins installed in the IC tester can be tested. For example, in case where the IC tester has a hundred test pins, an IC device having less than 50 I/O pins can be tested under the double speed testing. That is, only the half number of test pins of the IC tester can be fully used.